The present invention relates to a method of delaying a binary periodic input signal using at least two series-connected semiconductor type delay devices of variable delay, and delaying the input signal successively in the series-connected delay devices, said delay devices being connected to a control means and each producing a respective output signal. The invention also relates to an arrangement for carrying out the method.
Periodic binary data signals are often used as clock signals, in which case very high demands are placed on a well-defined frequency. There is often a reason to multiply the frequency of a clock signal in order to obtain a new clock signal of higher frequency. A clock signal can be frequency multiplied by using delayed signals of an original clock signal and combining the delayed signals in a logic circuit in some suitable manner to provide a clock signal of higher frequency. One problem in this regard is that the delayed signals are not delayed accurately enough. When the delayed signals are used to extract desired signals, the deficiency in delay accuracy is propagated, thereby resulting in error in the multiplied clock signal, for instance in the form of an uneven pulse-pause-ratio. A resume of how delayed clock signals have earlier been obtained and how frequency multiplied circuits have been produced is given below.
An article "Unsurpassed Flexibility Heralds Clock Generator" by Dave Bursky on pages 63-66 of the technical magazine Electronic Design, Nov. 12 1992, describes a circuit for generating clock frequencies. The circuit includes a phase-locked loop which comprises a phase detector, a filter, a voltage controlled oscillator, and a division circuit. The phase detector compares the respective phases of a reference signal and a feedback signal from the voltage controlled oscillator and delivers a control signal to the filter, which in turn delivers a control voltage to the oscillator. There is then produced on the oscillator output a signal which is received and divided by the division circuit, so that the divided signal obtains the same frequency as the reference signal. The voltage controlled oscillator is a ring oscillator which includes a plurality of series-connected delay elements of variable delay. Signals are tapped from the delay elements to a programmable matrix selector. The matrix selector can be programmed to provide signals whose frequencies are multiples of the reference signal frequency or signals which are delayed in relation to the reference signal.
United Kingdom Patent Application G. B. 2,199,457 A teaches a circuit for doubling the frequency of an incoming binary data signal. The data signal is delayed in a variable delay device. The data signal and the delayed data signal are then combined logically in a circuit which therewith produces an output signal whose frequency is twice that of the input signal. The output signal and the input signal are used to adjust the delay of the delay device so as to obtain a 50/50 pulse-pause-ratio.
United Kingdom Patent Application G. B. 2,130,825 A teaches a delay circuit which includes a plurality of series-connected transistors constructed in so-called I.sup.2 L-technique. A phase comparator compares the phase of an input signal with the phase of a delayed input signal. The delay of each transistor is corrected on the basis of this phase comparison, so as to obtain the desired delay.
United Kingdom Patent Specification G. B. 1,561,465 teaches a circuit for changing the frequency of an input signal. The input signal is first frequency-divided in a division circuit and then delayed in a delay circuit which comprises series-connected delay elements having several tapping points. The divided signal and the plurality of delayed signals are combined logically in a logic circuit, so as to obtain an output signal of desired frequency.
IBM Technical Disclosure Bulletin, Vol. 34, No. 3, August 1991, teaches a circuit for doubling the frequency of an input signal. The input signal is delayed in a delay device whose delay can be adjusted with a control voltage. The input signal and the delayed signal are combined in a logic circuit, so as to obtain a signal whose frequency is twice that of the input signal frequency. This signal and the delayed input signal are converted in a circuit, which converts the pulse-pause-ratio of the signal to voltages. These two voltages are compared in a comparator which produces the control voltage that adjusts the delay of the delay device.
Japanese Patent Publication JP 61-16 37 15 (A) teaches series-connected delay elements 1 which are used to obtain so-called multi-phase blocks. The delay elements produce delayed signals and each delayed signal is combined logically with an inverted delayed signal in a two-input AND-gate. The output signals are then used for multi-phase clocks.
Although the aforesaid publications present solutions to the problem of multiplying the frequency of a clock signal and of delaying a clock signal, the problem of generating the delayed signals that are used to extract the multiplied signal with sufficiently high accuracy still remains.